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ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 1 post office box 655303 ? dallas, texas 75265 member of the pin-compatible commsdac ? product family 125 msps update rate 14-bit resolution spurious free dynamic range (sfdr) to nyquist at 40 mhz output: 63 dbc 1 ns setup/hold time differential scalable current outputs: 2 ma to 20 ma on-chip 1.2 v reference 3 v and 5 v cmos-compatible digital interface straight binary or twos complement input power dissipation: 175 mw at 5 v, sleep mode: 25 mw at 5 v package: 28-pin soic and tssop description the ths5671a is a 14-bit resolution digital-to-analog converter (dac) specifically optimized for digital data transmission in wired and wireless communication systems. the 14-bit dac is a member of the commsdac series of high-speed, low-power cmos digital-to-analog converters. the commsdac family consists of pin compatible 14-, 12-, 10-, and 8-bit dacs. all devices offer identical interface options, small outline package, and pinout. the ths5671a offers superior ac and dc performance while supporting update rates up to 125 msps. the ths5671a operates from an analog supply of 4.5 v to 5.5 v. its inherent low power dissipation of 175 mw ensures that the device is well-suited for portable and low-power applications. lowering the full-scale current output reduces the power dissipation without significantly degrading performance. the device features a sleep mode, which reduces the standby power to approximately 25 mw, thereby optimizing the power consumption for system needs. the ths5671a is manufactured in texas instruments advanced high-speed mixed-signal cmos process. a current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. on-chip edge-triggered input latches and a 1.2 v temperature-compensated bandgap reference provide a complete monolithic dac solution. the digital supply range of 3 v to 5.5 v supports 3 v and 5 v cmos logic families. minimum data input setup and hold times allow for easy interfacing with external logic. the ths5671a supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors. the ths5671a provides a nominal full-scale differential output current of 20 ma and >300 k ? output impedance, supporting both single-ended and differential applications. the output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. an accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 ma down to 2 ma, with no significant degradation of performance. this reduces power consumption and provides 20 db gain range control capabilities. alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying dac. the output voltage compliance range is 1.25 v. copyright ? 2002, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clk dv dd dgnd mode av dd comp2 iout1 iout2 agnd comp1 biasj extio extlo sleep soic (dw) or tssop (pw) package (top view) commsdac is a trademark of texas instruments incorporated.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 2 post office box 655303 ? dallas, texas 75265 description (continued) the ths5671a is available in both a 28-pin soic and tssop package. the device is characterized for operation over the industrial temperature range of ? 40 c to 85 c. available options package t a 28-tssop (pw) 28-soic (dw) ? 40 c to 85 c ths5671aipw ths5671aidw functional block diagram iout1 iout2 clk d[13:0] extlo dgnd av dd extio comp2 current source array output current switches agnd 1.2 v ref biasj ? + control amp 0.1 f 2 k ? i bias comp1 logic control 50 ? 1 nf dv dd r bias sleep mode r load r load c ext c 1 0.1 f 0.1 f 50 ?
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description agnd 20 i analog ground return for the internal analog circuitry av dd 24 i positive analog supply voltage (4.5 v to 5.5 v) biasj 18 o full-scale output current bias clk 28 i external clock input. input data latched on rising edge of the clock. comp1 19 i compensation and decoupling node, requires a 0.1 f capacitor to av dd . comp2 23 i internal bias node, requires a 0.1 f decoupling capacitor to agnd. d[13:0] [1:14] i data bits 0 through 13. d13 is most significant data bit (msb), d0 is least significant data bit (lsb). dgnd 26 i digital ground return for the internal digital logic circuitry dv dd 27 i positive digital supply voltage (3 v to 5.5 v) extio 17 i/o used as external reference input when internal reference is disabled (i.e., extlo = av dd ). used as internal reference output when extlo = agnd, requires a 0.1 f decoupling capacitor to agnd when used as reference output. extlo 16 o internal reference ground. connect to av dd to disable the internal reference source. iout1 22 o dac current output. full scale when all input bits are set 1 iout2 21 o complementary dac current output. full scale when all input bits are 0 mode 25 i mode select. internal pulldown. mode 0 is selected if this pin is left floating or connected to dgnd. see timing diagram. sleep 15 i asynchronous hardware power down input. active high. internal pulldown. requires 5 s to power down but 3 ms to power up. absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage range, av dd (see note 1) ? 0.3 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv dd (see note 2) ? 0.3 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage between agnd and dgnd ? 0.3 v to 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, av dd to dv dd ? 6.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clk, sleep, mode (see note 2) ? 0.3 v to dv dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . digital input d13 ? d0 (see note 2) ? 0.3 v to dv dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . iout1, iout2 (see note 1) ? 1 v to av dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . comp1, comp2 (see note 1) ? 0.3 v to av dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . extio, biasj (see note 1) ? 0.3 v to av dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . extlo (see note 1) ? 0.3 v to 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak input current (any input) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak total input current (all inputs) ? 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : ths5671ai ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. measured with respect to agnd. 2. measured with respect to dgnd.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 4 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, av dd = 5 v, dv dd = 5 v, iout fs = 20 ma (unless otherwise noted) dc specifications parameter test conditions min typ max unit resolution 14 bits dc accuracy ? inl integral nonlinearity t a = 40 cto85 c ? 7 2.5 7 lsb dnl differential nonlinearity t a = ? 40 c to 85 c ? 3.5 2 3.5 lsb monotonicity at 11-bit level monotonic analog output offset error 0.02 %fsr gain error without internal reference 2.3 %fsr gain error with internal reference 1.3 %fsr full scale output current ? 2 20 ma output compliance range av dd = 5 v, iout fs = 20 ma ? 1 1.25 v output resistance 300 k ? output capacitance 5 pf reference output reference voltage 1.18 1.22 1.32 v reference output current 100 na reference input v extio input voltage range 0.1 1.25 v input resistance 1 m ? small signal bandwidth ? without c comp1 1.3 mhz input capacitance 100 pf temperature coefficients offset drift 0 gain drift without internal reference 40 ppm of gain drift with internal reference 120 m of fsr/ c reference voltage drift 35 power supply av dd analog supply voltage 4.5 5 5.5 v dv dd digital supply voltage 3 5.5 v i avdd analog supply current 25 30 ma i avdd sleep mode supply current sleep mode 3 5 ma i dvdd digital supply current # 5 6 ma power dissipation || av dd = 5 v, dv dd = 5 v, iout fs = 20 ma 175 mw av dd power su pp ly rejection ratio 0.4 %fsr/v dv dd power supply rejection ratio 0.025 %fsr/v operating range ? 40 85 c ? measured at iout1 in virtual ground configuration. ? nominal full-scale current iout fs equals 32x the ibias current. use an external buffer amplifier with high impedance input to drive any external load. ? reference bandwidth is a function of external cap at comp1 pin and signal level. # measured at f clk = 50 msps and f out = 1 mhz. || measured for 50 ? r load at iout1 and iout2, f clk = 50 msps and f out = 20 mhz. specifications subject to change
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, av dd = 5 v, dv dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load (unless otherwise noted) ac specifications parameter test conditions min typ max unit analog output f clk maximum out p ut u p date rate dv dd = 4.5 v to 5.5 v 100 125 msps f clk maximum output update rate dv dd = 3 v to 3.6 v 70 100 msps t s(dac) output settling time to 0.1% ? 35 ns t pd output propagation delay 1 ns ge glitch energy ? worst case lsb transition (code 8191 ? code 8192) 5 pv-s t r(iout) output rise time 10% to 90% ? 1 ns t f(iout) output fall time 90% to 10% ? 1 ns out p ut noise iout fs = 20 ma 15 pa/ hz output noise iout fs = 2 ma 10 p a/ hz ac linearity f clk = 25 msps, f out = 1 mhz, t a = 25 c ? 74 thd total harmonic distortion f clk = 50 msps, f out = 1 mhz, t a = ? 40 c to 85 c ? 73 ? 66 dbc thd total harmonic distortion f clk = 50 msps, f out = 2 mhz, t a = 25 c ? 71 dbc f clk = 100 msps, f out = 2 mhz, t a = 25 c ? 71 f clk = 25 msps, f out = 1 mhz, t a = 25 c 82 f clk = 50 msps, f out = 1 mhz, t a = ? 40 c to 85 c 68 f clk = 50 msps, f out = 1 mhz, t a = 25 c 82 dbc spurious free dynamic range to f clk = 50 msps, f out = 2.51 mhz, t a = 25 c 75 dbc s pur i ous f ree d ynam i c range t o nyquist f clk = 50 msps, f out = 5.02 mhz, t a = 25 c 74 sfdr nyquist f clk = 50 msps, f out = 20.2 mhz, t a = 25 c 57 sfdr f clk = 100 msps, f out = 5.04 mhz, t a = 25 c 70 dbc f clk = 100 msps, f out = 20.2 mhz, t a = 25 c 66 dbc f clk = 100 msps, f out = 40.4 mhz, t a = 25 c 63 dbc spurious free dynamic range f clk = 50 msps, f out = 1 mhz, t a = 25 c,1 mhz span 90 s pur i ous f ree d ynam i c range within a window f clk = 50 msps, f out = 5.02 mhz, 2 mhz span 89 dbc within a window f clk = 100 msps, f out = 5.04 mhz, 4 mhz span 89 ? measured single ended into 50 ? load at iout1. ? single-ended output iout1, 50 ? doubly terminated load. measured with a 50%/50% duty cycle (high/low percentage of the clock). optimum ac linearity is obtained when limiting the duty cycle to a range from 45%/55% to 55%/45%.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, av dd = 5 v, dv dd = 5 v, iout fs = 20 ma (unless otherwise noted) digital specifications parameter test conditions min typ max unit interface v ih high level in p ut voltage dv dd = 5 v 3.5 5 v v ih high - level input voltage dv dd = 3.3 v 2.1 3.3 v v il low level in p ut voltage dv dd = 5 v 0 1.3 v v il low - level input voltage dv dd = 3.3 v 0 0.9 v i ih high level in p ut current mode and sleep dv dd = 3 v to 5.5 v ? 15 15 a i ih high - level input current all other digital pins dv dd = 3 v to 5.5 v ? 10 10 a i il low level in p ut current mode and sleep dv dd = 3 v to 5.5 v ? 15 15 a i il low - level input current all other digital pins dv dd = 3 v to 5.5 v ? 10 10 a c i input capacitance 1 5 pf timing t su(d) input setup time 1 ns t h(d) input hold time 1 ns t w(lph) input latch pulse high time 4 ns t d(d) digital delay time 1 clk specifications subject to change
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 7 post office box 655303 ? dallas, texas 75265 typical characteristics ? 48 54 60 66 72 78 84 90 0 1020304050 figure 1 spurious free dynamic range vs output frequency at 0 dbfs f out ? output frequency ? mhz f clk = 5 msps sfdr ? spurious free dynamic range ? dbc f clk = 50 msps f clk = 70 msps dv dd = 5 v f clk = 25 msps f clk = 100 msps f clk = 125 msps figure 2 60 66 72 78 84 90 0 0.5 1.0 1.5 2.0 2.5 spurious free dynamic range vs output frequency at 5 msps f out ? output frequency ? mhz 0 dbfs sfdr ? spurious free dynamic range ? dbc ? 6 dbfs ? 12 dbfs dv dd = 5 v 60 66 72 78 84 90 024681012 figure 3 spurious free dynamic range vs output frequency at 25 msps f out ? output frequency ? mhz ? 6 dbfs sfdr ? spurious free dynamic range ? dbc ? 12 dbfs 0 dbfs dv dd = 5 v 48 54 60 66 72 78 0 5 10 15 20 25 figure 4 spurious free dynamic range vs output frequency at 50 msps f out ? output frequency ? mhz ? 6 dbfs sfdr ? spurious free dynamic range ? dbc ? 12 dbfs 0 dbfs dv dd = 5 v ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 8 post office box 655303 ? dallas, texas 75265 typical characteristics ? 48 54 60 66 72 78 0 10203040 figure 5 spurious free dynamic range vs output frequency at 70 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc ? 12 dbfs ? 6 dbfs 0 dbfs dv dd = 5 v figure 6 48 54 60 66 72 78 0 1020304050 spurious free dynamic range vs output frequency at 100 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc ? 12 dbfs ? 6 dbfs 0 dbfs dv dd = 5 v 48 54 60 66 72 78 0 1020304050 figure 7 spurious free dynamic range vs output frequency at 125 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 5 v ? 12 dbfs ? 6 dbfs 0 dbfs 42 48 54 60 66 72 78 84 90 0 10203040 figure 8 spurious free dynamic range vs output frequency at 0 dbfs f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 3.3 v f clk = 5 msps f clk = 50 msps f clk = 25 msps f clk = 100 msps ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 9 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 9 60 66 72 78 84 90 0 0.5 1.0 1.5 2.0 spurious free dynamic range vs output frequency at 5 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 3.3 v ? 12 dbfs ? 6 dbfs 0 dbfs 60 66 72 78 84 90 0246810 figure 10 spurious free dynamic range vs output frequency at 25 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 3.3 v ? 12 dbfs 0 dbfs ? 6 dbfs figure 11 48 54 60 66 72 78 0 5 10 15 20 25 spurious free dynamic range vs output frequency at 50 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 3.3 v ? 12 dbfs ? 6 dbfs 0 dbfs 48 54 60 66 72 78 0 10203040 figure 12 spurious free dynamic range vs output frequency at 70 msps f out ? output frequency ? mhz sfdr ? spurious free dynamic range ? dbc dv dd = 3.3 v ? 12 dbfs ? 6 dbfs 0 dbfs ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 10 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 13 48 54 60 66 72 78 84 ? 27 ? 24 ? 21 ? 18 ? 15 ? 12 ? 9 ? 6 ? 30 spurious free dynamic range vs a out at f out = f clock /11 a out ? dbfs 2.27 mhz @ 25 msps sfdr ? spurious free dynamic range ? dbc dv dd = 5 v 4.55 mhz @ 50 msps 6.36 mhz @ 70 msps 9.1 mhz @ 100 msps figure 14 48 54 60 66 72 78 84 ? 27 ? 24 ? 21 ? 18 ? 15 ? 12 ? 9 ? 6 ? 30 spurious free dynamic range vs a out at f out = f clock/5 a out ? dbfs sfdr ? spurious free dynamic range ? dbc dv dd = 5 v 20 mhz @ 100 msps 5 mhz @ 25 msps 10 mhz @ 50 msps 14 mhz @ 70 msps figure 15 48 54 60 66 72 78 84 ? 27 ? 24 ? 21 ? 18 ? 15 ? 12 ? 9 ? 6 ? 30 dual tone spurious free dynamic range vs a out at f out = f clock/7 a out ? dbfs sfdr ? spurious free dynamic range ? dbc dv dd = 5 v 0.675/0.725 mhz @ 5 msps 3.38/3.63 mhz @ 25 msps 6.75/7.25 mhz @ 50 msps 9.67/10.43 mhz @ 70 msps 13.5/14.5 mhz @ 100 msps figure 16 ? 90 ? 84 ? 78 ? 72 ? 66 0 20406080100120 total harmonic distortion vs clock frequency at f out = 2 mhz f clock ? clock frequency ? msps 2nd harmonic thd ? total harmonic distortion ? dbc dv dd = 5 v 3rd harmonic 4th harmonic ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 11 post office box 655303 ? dallas, texas 75265 typical characteristics ? 48 54 60 66 72 78 84 2 4 6 8 101214161820 sfdr ? spurious free dynamic range ? dbc f out = 10 mhz f out = 40 mhz dv dd = 5 v iout fs ? full-scale output current ? ma f out = 28.6 mhz figure 17 spurious free dynamic range vs full-scale output current at 100 msps f out = 2.5 mhz figure 18 42 48 54 60 66 72 78 84 0 5 10 15 20 25 30 35 40 45 50 spurious free dynamic range vs output frequency at 100 msps f out ? output frequency ? mhz diff @ 0 dbfs sfdr ? spurious free dynamic range ? dbc diff @ ? 6 dbfs iout1 @ ? 6 dbfs iout1 @ 0 dbfs dv dd = 5 v figure 19 48 54 60 66 72 78 84 ? 40 ? 200 20406080 spurious free dynamic range vs temperature at 70 msps t a ? temperature ? c f out = 2 mhz sfdr ? spurious free dynamic range ? dbc f out = 10 mhz f out = 25 mhz dv dd = 5 v ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 12 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 20 inl ? integral nonlinearity ? lsb code integral nonlinearity ? 4 ? 2 0 2 4 0 2048 4096 6144 8192 10240 12288 14336 16384 figure 21 dnl ? differential nonlinearity ? lsb code differential nonlinearity ? 2 ? 1 0 1 0 2048 4096 6144 8192 10240 12288 14336 16384 ? 3 ? 4 figure 22 amplitude ? dbm single-tone output spectrum ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0 5 10 15 20 25 f out = 5 mhz at f clock = 50 msps, dv dd = 5 v frequency ? mhz ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 13 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 23 amplitude ? dbm single-tone output spectrum ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0 1020304050 f out = 10 mhz at f clock = 100 msps, dv dd = 5 v frequency ? mhz figure 24 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0 1020304050 amplitude ? dbm frequency ? mhz dual-tone output spectrum f clock = 100 msps f out1 = 13.2 mhz, f out2 = 14.2 mhz, dv dd = 5 v figure 25 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0 5 10 15 20 25 amplitude ? dbm frequency ? mhz four-tone output spectrum f clock = 50 msps f out1 = 6.25 mhz, f out2 = 6.75 mhz, f out3 = 7.25 mhz, f out4 = 7.75 mhz, dv dd = 5 v ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 14 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 26 0 5 10 15 20 25 30 2 4 6 8 101214161820 supply current vs full-scale output current iout fs ? full-scale output current ? ma i(avdd) ? supply current ? ma dv dd = 5 v figure 27 0 5 10 15 20 25 0 0.1 0.2 0.3 0.4 0.5 digital supply current vs ratio (fclock/fout) at dv dd = 5 v ratio ? (fclock/fout) 100 msps i(dvdd) ? supply current ? ma 70 msps 50 msps 25 msps 5 msps figure 28 0 2 4 6 8 10 0 0.1 0.2 0.3 0.4 0.5 5 msps digital supply current vs ratio (fclock/fout) at dv dd = 3.3 v ratio ? (fclock/fout) i(dvdd) ? supply current ? ma 25 msps 50 msps 70 msps ? av dd = 5 v, iout fs = 20 ma, differential transformer coupled output, 50 ? doubly terminated load, t a = 25 c (unless otherwise noted.)
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 15 post office box 655303 ? dallas, texas 75265 application information the ths5671a architecture is based on current steering, combining high update rates with low power consumption. the cmos device consists of a segmented array of pmos transistor current sources, which are capable of delivering a full-scale current up to 20 ma. high-speed differential current switches direct the current of each current source to either one of the output nodes, iout1 or iout2. the complementary output currents thus enable differential operation, canceling out common mode noise sources (on-chip and pcb noise), dc offsets, even order distortion components, and increases signal output power by a factor of two. major advantages of the segmented architecture are minimum glitch energy, excellent dnl, and very good dynamic performance. the dac ? s high output impedance of >300 k ? and fast switching result in excellent dynamic linearity (spurious free dynamic range sfdr). the full-scale output current is set using an external resistor r bias in combination with an on-chip bandgap voltage reference source (1.2 v) and control amplifier. the current i bias through resistor r bias is mirrored internally to provide a full-scale output current equal to 32 times i bias . the full-scale current can be adjusted from 20 ma down to 2 ma. data interface and timing the ths5671a comprises separate analog and digital supplies, i.e. av dd and dv dd . the digital supply voltage can be set from 5.5 v down to 3 v, thus enabling flexible interfacing with external logic. the ths5671a provides two operating modes, as shown in table 1. mode 0 (mode pin connected to dgnd) supports a straight binary input data word format, whereas mode 1 (mode pin connected to dv dd ) sets a twos complement input configuration. figure 29 shows the timing diagram. internal edge-triggered flip-flops latch the input word on the rising edge of the input clock. the ths5671a provides for minimum setup and hold times (> 1 ns), allowing for noncritical external interface timing. conversion latency is one clock cycle for both modes. the clock duty cycle can be chosen arbitrarily under the timing constraints listed in the digital specifications table. however, a 50% duty cycle will give optimum dynamic performance. figure 30 shows a schematic of the equivalent digital inputs of the ths5671a, valid for pins d13 ? d0, sleep, and clk. the digital inputs are cmos-compatible with logic thresholds of dv dd /2 20%. since the ths5671a is capable of being updated up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the ths5671a, as well as its required min/max input logic level thresholds. typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feed-through and noise. additionally, operating the ths5671a with reduced logic swings and a corresponding digital supply (dv dd ) will reduce data feed-through. note that the update rate is limited to 70 msps for a digital supply voltage dv dd of 3 v to 3.6 v.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 16 post office box 655303 ? dallas, texas 75265 application information data interface and timing (continued) clk d[13:0] dac output (iout1 or iout2) t w(lph) t d(d) 0.1% 0.1% 50% t h(d) valid data t su(d) t pd t s(dac) 1/f clk t r(iout) 90% 10% 50% 50% 50% 50% figure 29. timing diagram table 1. input interface modes mode 0 mode 1 function/mode mode pin connected to dgnd mode pin connected to dv dd input code format binary twos complement external digital in internal digital in dv dd figure 30. digital equivalent input
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 17 post office box 655303 ? dallas, texas 75265 application information dac transfer function the ths5671a delivers complementary output currents iout1 and iout2. output current iout1 equals the approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the binary input word has the decimal representation 16383. for mode 1, the msb is inverted (twos complement input format). full-scale output current will flow through terminal iout2 when all input bits are set low (mode 0, straight binary input). the relation between iout1 and iout2 can thus be expressed as: iout1 iout fs iout2 where iout fs is the full-scale output current. the output currents can be expressed as: iout1 iout fs code 16384 iout2 iout fs (16383 code) 16384 where code is the decimal representation of the dac data input word. output currents iout1 and iout2 drive resistor loads r load or a transformer with equivalent input load resistance r load . this would translate into single-ended voltages vout1 and vout2 at terminal iout1 and iout2, respectively, of: vout1 iout1 r load code 16384 iout fs r load vout2 iout2 r load (16383 ? code) 16384 iout fs r load the differential output voltage vout diff can thus be expressed as: vout diff vout1 ? vout2 (2code ? 16383) 16384 iout fs r load the latter equation shows that applying the differential output will result in doubling of the signal power delivered to the load. since the output currents of iout1 and iout2 are complementary, they become additive when processed differentially. care should be taken not to exceed the compliance voltages at node iout1 and iout2, which would lead to increased signal distortion.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 18 post office box 655303 ? dallas, texas 75265 application information reference operation the ths5671a comprises a bandgap reference and control amplifier for biasing the full-scale output current. the full-scale output current is set by applying an external resistor r bias . the bias current i bias through resistor r bias is defined by the on-chip bandgap reference voltage and control amplifier. the full-scale output current equals 32 times this bias current. the full-scale output current iout fs can thus be expressed as: iout fs 32 i bias 32 v extio r bias where v extio is the voltage at terminal extio. the bandgap reference voltage delivers an accurate voltage of 1.2 v. this reference is active when terminal extlo is connected to agnd. an external decoupling capacitor c ext of 0.1 f should be connected externally to terminal extio for compensation. the bandgap reference can additionally be used for external reference operation. in that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 na. the internal reference can be disabled and overridden by an external reference by connecting extlo to av dd . capacitor c ext may hence be omitted. terminal extio thus serves as either input or output node. the full-scale output current can be adjusted from 20 ma down to 2 ma by varying resistor r bias or changing the externally applied reference voltage. the internal control amplifier has a wide input range, supporting the full-scale output current range of 20 db. the bandwidth of the internal control amplifier is defined by the internal 1 nf compensation capacitor at pin comp1 and the external compensation capacitor c1. the relatively weak internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal 1 nf load, as shown in figure 31. this provides the user with more flexibility and higher bandwidths, which are specifically attractive for gain control and multiplying dac applications. pin sleep should be connected to agnd or left disconnected when an external control amplifier is used. av dd 1.2 v ref ref amp 1 nf + ? + ? avdd agnd extlo extio biasj av dd iout1 or iout2 external control amp ext reference voltage comp1 sleep current source array r ext internal control amp ths4041 figure 31. bypassing the internal reference and control amplifier
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 19 post office box 655303 ? dallas, texas 75265 application information analog current outputs figure 32 shows a simplified schematic of the current source array output with corresponding switches. differential pmos switches direct the current of each individual pmos current source to either the positive output node iout1 or its complementary negative output node iout2. the output impedance is determined by the stack of the current sources and differential switches, and is typically >300 k ? in parallel with an output capacitance of 5 pf. output nodes iout1 and iout2 have a negative compliance voltage of ? 1 v, determined by the cmos process. beyond this value, transistor breakdown may occur, resulting in reduced reliability of the ths5671a device. the positive output compliance depends on the full-scale output current iout fs and positive supply voltage av dd . the positive output compliance equals 1.25 v for av dd = 5 v and iout fs = 20 ma. exceeding the positive compliance voltage adversely affects distortion performance and integral nonlinearity. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at iout1 and iout2 does not exceed 0.5 v (e.g. when applying a 50 ? doubly terminated load for 20 ma full-scale output current). applications requiring the ths5671a output (i.e., out1 and/or out2) to extend its output compliance should size r load accordingly. av dd current source array iout1 iout2 r load r load current sources switches figure 32. equivalent analog current output figure 33(a) shows the typical differential output configuration with two external matched resistor loads. the nominal resistor load of 50 ? will give a differential output swing of 2 v pp when applying a 20 ma full-scale output current. the output impedance of the ths5671a depends slightly on the output voltage at nodes iout1 and iout2. consequently, for optimum dc integral nonlinearity, the configuration of figure 33(b) should be chosen. in this i ? v configuration, terminal iout1 is kept at virtual ground by the inverting operational amplifier. the complementary output should be connected to ground to provide a dc current path for the current sources switched to iout2. note that the inl/dnl specifications for the ths5671a are measured with iout1 maintained at virtual ground. the amplifier ? s maximum output swing and the dac ? s full-scale output current determine the value of the feedback resistor r fb . capacitor c fb filters the steep edges of the ths5671a current output, thereby reducing the operational amplifier slew-rate requirements. in this configuration, the op amp should operate on a dual supply voltage due to its positive and negative output swing. node iout1 should be selected if a single-ended unipolar output is desirable.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 20 post office box 655303 ? dallas, texas 75265 application information iout2 iout1 iout2 iout1 vout 100 ? ? + r fb +) ? ) vout +) ? ) 50 ? (a) (b) 50 ? c fb ths4001 ths4011 figure 33. differential and single-ended output configuration the ths5671a can be easily configured to drive a doubly terminated 50- ? cable. figure 34(a) shows the single-ended output configuration, where the output current iout1 flows into an equivalent load resistance of 25 ? . node iout2 should be connected to ground or terminated with a resistor of 25 ? . differential-to-single conversion (e.g., for measurement purposes) can be performed using a properly selected rf transformer, as shown in figure 34(b). this configuration provides maximum rejection of common-mode noise sources and even order distortion components, thereby doubling the power to the output. the center tap on the primary side of the transformer is connected to agnd, enabling a dc current flow for both iout1 and iout2. note that the ac performance of the ths5671a is optimum and specified using this differential transformer coupled output, limiting the voltage swing at iout1 and iout2 to 0.5 v. iout2 iout1 vout iout2 iout1 vout 50 ? 100 ? (a) (b) 25 ? 50 ? 50 ? 50 ? 50 ? 1:1 figure 34. driving a doubly terminated 50- ? cable
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 21 post office box 655303 ? dallas, texas 75265 application information sleep mode the ths5671a features a power-down mode that turns off the output current and reduces the supply current to less than 5 ma over the analog supply range of 4.5 v to 5.5 v and temperature range. the power-down mode is activated by applying a logic level 1 to the sleep pin (e.g., by connecting pin sleep to avdd). an internal pulldown circuit at node sleep ensures that the ths5671a is enabled if the input is left disconnected. power-up and power-down activation times depend on the value of external capacitor at node sleep. for a nominal capacitor value of 0.1 f power down takes less than 5 s, and approximately 3 ms to power backup. the sleep mode should not be used when an external control amplifier is used, as shown in figure 31. definitions of specifications and terminology integral nonlinearity (inl) the relative accuracy or integral nonlinearity (inl), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (dnl) the differential nonlinearity (dnl), sometimes referred to as differential error, is the difference between the measured and ideal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. offset error offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0. gain error gain error is the error in slope of the dac transfer function. signal-to-noise ratio + distortion (s/n+d or sinad) s/n+d or sinad is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. spurious free dynamic range (sfdr) sfdr is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. the value for sfdr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. output compliance range the maximum and minimum allowable voltage of the output of the dac, beyond which either saturation of the output stage or breakdown may occur. settling time the time required for the output to settle within a specified error band. glitch energy the time integral of the analog value of the glitch transient.
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 22 post office box 655303 ? dallas, texas 75265 application information definitions of specifications and terminology (continued) offset drift the change in offset error versus temperature from the ambient temperature (t a = 25 c) in ppm of full-scale range per c. gain drift the change in gain error versus temperature from the ambient temperature (t a = 25 c) in ppm of full-scale range per c. reference voltage drift the change in reference voltage error versus temperature from the ambient temperature (t a = 25 c) in ppm of full-scale range per c. ths5671a evaluation board an evaluation module (evm) board for the ths5671a digital-to-analog converter is available for evaluation. this board allows the user the flexibility to operate the ths5671a in various configurations. possible output configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs. the digital inputs are designed to interface with the tms320 c5000 or c6000 family of dsps or to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination. see the ths56x1 evaluation module user?s guide for more details (slau032).
ths5671a 14-bit, 125 msps, commsdac digital-to-analog converter slas201a ? december 1999 ? revised september 2002 ? post office box 655303 dallas, texas 75265 ? 23 ? 5va d2 10 d3 9 d4 8 d5 7 d6 6 d7 5 d8 4 d9 3 d10 2 d11 1 clk 28 mode 25 dvdd 27 dgnd 26 agnd 20 avdd 24 extlo 16 extio 17 biasj 18 comp1 19 comp2 23 iout1 22 iout2 21 sleep 15 11 12 d1 13 d0 14 u5 ths5671a fb3 c12 0.1 f + c18 4.7 f +5va j8 r24 49.9 j9 r29 49.9 dac[2..15] dac2 dac3 dac4 dac5 dac6 dac7 dac8 dac9 dac10 dac11 dac12 dac13 dac14 dac15 dsp[2..15] r4a r10a r10b r10c r10d r10e r10f r10g r4b r10h r11a r11b r11c r11d r11e r11f r11g r11h r5g r5f r5e r5h r4e r4c r4d r4f r4g r4h r5a r5b r5c r5d t1 t1 ? 1t ? kk81 r25 tdb ~oe a0 a1 r20 10 k r18 49.9 j5 w5 dsp2 dsp3 dsp4 dvdcc dsp5 +5va dsp6 w3 dsp7 dsp8 dsp9 dsp10 dsp11 dsp12 dsp13 dsp14 clkout dsp15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 j1 c17 0.1 f w4 r14 5 k c13 0.1 f c16 0.1 f r2 0 ? c32 c25 clkout dsp0 dsp1 ~oe c11 0.1 f dvdcc w2 dvdcc r6 10k r3 10 k dvdcc dsp0 dsp1 dsp2 dsp3 dsp4 dsp5 dsp6 dsp7 dsp8 dsp9 dsp10 dsp11 dsp12 dsp13 dsp14 dsp15 dac0 dac1 dac2 dac3 dac4 dac5 dac6 dac7 dac8 dac9 dac10 dac11 dac12 dac13 dac14 dac15 oe 19 dir 1 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 b1 18 b2 17 b3 16 b4 15 b5 14 b6 13 b7 12 b8 11 vcc 20 gnd 10 u2 sn74lvt245b oe 19 dir 1 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 b1 18 b2 17 b3 16 b4 15 b5 14 b6 13 b7 12 b8 11 vcc 20 gnd 10 u1 sn74lvt245b 1 3 1 3 r23 100 j6 r12 33 r9 33 r7 33 u6a sn74alvc08 5 3 u4 sn74hc1g32 c5 0.1 f + c4 10 f c1 1 f c3 0.1 f c2 0.01 f c23 0.1 f + c24 10 f c31 1 f c30 0.1 f c29 0.01 f l1 l3 fb4 dvdcc +5va c7 0.1 f c6 0.1 f c10 0.1 f c8 0.1 f dvdcc miscellaniousdigital bypass caps 1 2 j2 d2 r16 3.0 k d1 r1 1.5 k w1 3 2 6 7 4 u9 ths3001 w6 w7 r30 750 r28 750 r26 750 r27 750 r22 10 j7 a b c d e f i/ostrobe pdac 5 3 u3 sn74ahc1g00 dvdcc dvdcc c9 0.1 f + c15 10 f c22 1 f c21 0.1 f 0.01 f l2 fb2 ? 5va 1 2 3 j4 +5va w8 w9 1 2 3 u8 ad1580brt r15 2.94 k r19 33 + c19 4.7 f c14 0.01 f 1 2 3 4 5 6 7 8 9 10 11 12 j3 u6b u6c u7 lt1004d alternateconfiguration + c35 4.7 f c34 0.1 f c33 0.01 f +5va + c28 4.7 f c27 0.1 f c26 0.01 f ? 5va u6d r13 r8 r17 r21 0 ? 4.7 h 4.7 h 4.7 h 1 3 0 ? 0 ? 0 ? figure 35. schematic application information d12 d13 fb1 c20
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 24 post office box 655303 ? dallas, texas 75265 application information figure 36. board layout, layer 1 figure 37. board layout, layer 2
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 25 post office box 655303 ? dallas, texas 75265 application information figure 38. board layout, layer 3 figure 39. board layout, layer 4
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 26 post office box 655303 ? dallas, texas 75265 application information figure 40. board layout, layer 5 table 2. bill of materials qty ref. des part number description mfg. 3 c1, c22, c31 1206zc105kat2a ceranucm 1 f, 10 v, x7r, 10% avx 4 c18, c19, c28, c35 ecstojy475 6.3 v, 4.7 f, tantalum panasonic 3 c15, c24, c4 ecstojy106 6.3 v, 10 f, tantalum panasonic 0 c25, c32 ceramic, not installed, 50 v, x7r, 10% 6 c14, c2, c20, c26, c29, c33 12065c103kat2a ceramic, 0.01 f, 50 v, x7r, 10% avx 17 c10, c11, c12, c13, c16, c17, c21, c23, c27, c3, c30, c34, c5, c6, c7, c8, c9 12065c104kat2a ceramic, 0.1 f, 50 v, x7r, 10% avx 2 d1, d2 and/and5ga or equivalent green led, 1206 size sm chip led 4 fb1, fb2, fb3, fb4 27-43-037447 fair-rite sm beads #27-037447 fairrite 1 j1 tsw-117-07-l-d or equivalent 34-pin header for idc samtec 1 j2 krmz2 or equivalent 2 terminal screw connector, 2term_con lumberg 1 j3 tsw-112-07-l-s or equivalent single row 12-pin header samtec 1 j4 krmz3 or equivalent 3 terminal screw connector lumberg 3 j5, j6, j7 142-0701-206 or equivalent pcb mount sma jack, sma_pcb_mt johnson components 0 j8, j9 142-0701-206 or equivalent pcb mount sma jack, not installed johnson components 3 l1, l2, l3 do1608c-472 do1608c-series, ds1608c-472 coil craft 1 r1 1206 1206 chip resistor, 1.5k, 1/4 w, 1% 4 r10, r11, r4, r5 cts/cts766-163-(r)330-g-tr 8 element isolated resistor pack, 33 ?
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 27 post office box 655303 ? dallas, texas 75265 application information table 2. bill of materials (continued) qty ref. des part number description mfg. 4 r12, r19, r7, r9 1206 1206 chip resistor, 33 ? , 1/4 w, 1% 5 r13, r17. r2, r21, r8 1206 1206 chip resistor, 0 ? , 1/4 w, 1% 1 r14 3214w-1-502 e or equivalent 4 mm sm pot, 5k bourns 1 r15 1206 1206 chip resistor, 2.94k, 1/4 w, 1% 1 r16 1206 1206 chip resistor, 3k, 1/4 w, 1% 3 r18, r24, r29 1206 1206 chip resistor, 49.94k, 1/4 w, 1% 3 r20, r3, r6 1206 1206 chip resistor, 10k, 1/4 w, 1% 1 r22 1206 1206 chip resistor, 10k, 1/4 w, 1% 1 r23 1206 1206 chip resistor, 100k, 1/4 w, 1% 1 r25 1206 1206 chip resistor, tbd, 1/4 w, 1% 4 r26, r27, r28, r30 1206 1206 chip resistor, 750k, 1/4 w, 1% 1 t1 t1-1t-kk81 rf transformer, t1-1t-kk81 minicircuits 2 u1, u2 sn74lvt245bdw octal bus transceiver, 3-state, sn74lvt245b ti 1 u3 sn74ahct1g00dbvr/ sn74ahc1g00dbvr single gate nand, sn74ahc1g00 ti 1 u4 sn74ahct1g32dbvr/ sn74ahcc1g32dbvr single 2 input positive or gate, sn74ahc1g32 ti ths5641 ths5641idw dac, 3 ? 5.5 v, 8 bit, 100 msps ti ths5651a ths5651aidw dac, 3 ? 5.5 v, 10 bit, 125 msps ti ths5661a ths5661aidw dac, 3 ? 5.5 v, 12 bit, 125 msps ti ths5671a ths5671aidw dac, 3 ? 5.5 v, 14 bit, 125 msps ti 1 sn74alvc08 sn74alvc08d quad and gate ti 1 lt1004d lt1004cd-1-2/lt1004id-1-2 precision 1.2 v reference ti 0 not installed ad1580brt precision voltage reference, not installed 1 ths3001 ths3001cd/ths2001id ths3001 high-speed op amp ti 4 w2 tsw-102-07-l-s or equivalent 2 position jumper_.1 ?? spacing, w2 samtec 3 w3 tsw-102-07-l-s or equivalent 3 position jumper_.1 ?? spacing, w3 samtec 2 2x3_jumper tsw-102-07-l-s or equivalent 6-pin header dual row, 0.025 0.1, 2x3_jumper samtec
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 28 post office box 655303 ? dallas, texas 75265 mechanical data dw (r-pdso-g**) plastic small-outline package 16 pins shown 4040000 / e 08/01 seating plane 0.400 (10,15) 0.419 (10,65) 0.104 (2,65) max 1 0.012 (0,30) 0.004 (0,10) a 8 16 0.020 (0,51) 0.014 (0,35) 0.291 (7,39) 0.299 (7,59) 9 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) pins ** 0.010 (0,25) nom a max dim a min gage plane 20 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 16 0.600 24 0.610 (17,78) 28 0.700 (18,03) 0.710 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 ? 8 (11,51) (11,73) 0.453 0.462 18 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013
ths5671a 14-bit, 125 msps, commsdac ? digital-to-analog converter slas201a ? december 1999 ? revised september 2002 29 post office box 655303 ? dallas, texas 75265 mechanical data pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ths5671aidw active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ths5671aidwg4 active soic dw 28 20 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ths5671aidwr active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ths5671aidwrg4 active soic dw 28 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ths5671aipw active tssop pw 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ths5671aipwr active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ths5671aipwrg4 active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 8-aug-2005 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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